LIBRARY

UniformNoise

Generates uniform random noise in the range [l, u] at each clock tick.

Uses a seeded RNG for reproducibility: the same seed and simulation time produce the same output sequence.

Usage

DiscreteComponents.UniformNoise(l=0, u=1, seed=1)

Parameters:

Name	Description	Units	Default value
l	Lower bound	–	0
u	Upper bound	–	1
seed	RNG seed	–	1

Connectors

• y - This connector represents a real signal as an output from a component (RealOutput)

Variables

Name	Description	Units
td		–

Behavior

Source

"""
Generates uniform random noise in the range `[l, u]` at each clock tick.

Uses a seeded RNG for reproducibility: the same `seed` and simulation time
produce the same output sequence.
"""
component UniformNoise@[input clk extends Discrete]
  "Output signal"
  y = RealOutput@[clk]() {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": 1000, "y1": 450, "x2": 1100, "y2": 550, "rot": 0}
      },
      "tags": []
    }
  }
  sampler = DiscreteComponents.Sampler() {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": 450, "y1": 450, "x2": 550, "y2": 550, "rot": 0}
      },
      "tags": []
    }
  }
  continuousclock = BlockComponents.Sources.ContinuousClock() {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": 170, "y1": 450, "x2": 270, "y2": 550, "rot": 0}
      },
      "tags": []
    }
  }
  "Lower bound"
  parameter l::Real = 0
  "Upper bound"
  parameter u::Real = 1
  "RNG seed"
  parameter seed::Integer = 1
  variable td::Real
relations
  td@clk = sampler.y@clk
  y@clk = l + (u - l) * seeded_rand(seed, td)
  connect(continuousclock.y, sampler.u) {"Dyad": {"edges": [{"S": 1, "M": [], "E": 2}], "renderStyle": "standard"}}
metadata {"Dyad": {"icons": {"default": "dyad://DiscreteComponents/UniformNoise.svg"}}}
end

Flattened Source

"""
Generates uniform random noise in the range `[l, u]` at each clock tick.

Uses a seeded RNG for reproducibility: the same `seed` and simulation time
produce the same output sequence.
"""
component UniformNoise
  "Output signal"
  y = RealOutput@[clk]() {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": 1000, "y1": 450, "x2": 1100, "y2": 550, "rot": 0}
      },
      "tags": []
    }
  }
  sampler = DiscreteComponents.Sampler() {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": 450, "y1": 450, "x2": 550, "y2": 550, "rot": 0}
      },
      "tags": []
    }
  }
  continuousclock = BlockComponents.Sources.ContinuousClock() {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": 170, "y1": 450, "x2": 270, "y2": 550, "rot": 0}
      },
      "tags": []
    }
  }
  "Lower bound"
  parameter l::Real = 0
  "Upper bound"
  parameter u::Real = 1
  "RNG seed"
  parameter seed::Integer = 1
  variable td::Real
relations
  td@clk = sampler.y@clk
  y@clk = l + (u - l) * seeded_rand(seed, td)
  connect(continuousclock.y, sampler.u) {"Dyad": {"edges": [{"S": 1, "M": [], "E": 2}], "renderStyle": "standard"}}
metadata {"Dyad": {"icons": {"default": "dyad://DiscreteComponents/UniformNoise.svg"}}}
end

Test Cases

No test cases defined.

Related

• Examples

• Experiments

• Analyses

• Tests

  • TestUniformNoise