LIBRARY
Sampler ​
Clock-agnostic sampler block.
Samples an input, continuous signal u to a clocked, discrete signal y. The clock of y is inferred automatically, based on what it's connected to.
Usage ​
DiscreteComponents.Sampler()
Connectors ​
u- This connector represents a real signal as an input to a component (RealInput)y- This connector represents a real signal as an output from a component (RealOutput)
Behavior ​
Behavior of this component cannot be rendered because it includes path variables.
Source ​
dyad
"""
Clock-agnostic sampler block.
Samples an input, continuous signal `u` to a clocked, discrete signal `y`.
The clock of `y` is inferred automatically, based on what it's connected to.
"""
external component Sampler@[input inclk extends Continuous, input outclk extends Discrete]
u = RealInput@[inclk]() {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": -40, "y1": 450, "x2": 60, "y2": 550, "rot": 0}
},
"tags": []
}
}
y = RealOutput@[outclk]() {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": 960, "y1": 450, "x2": 1060, "y2": 550, "rot": 0}
},
"tags": []
}
}
relations
metadata {
"Dyad": {
"icons": {"default": "dyad://DiscreteComponents/Sampler.svg"},
"doc": {"behavior": false}
}
}
endFlattened Source
dyad
"""
Clock-agnostic sampler block.
Samples an input, continuous signal `u` to a clocked, discrete signal `y`.
The clock of `y` is inferred automatically, based on what it's connected to.
"""
external component Sampler
u = RealInput@[inclk]() {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": -40, "y1": 450, "x2": 60, "y2": 550, "rot": 0}
},
"tags": []
}
}
y = RealOutput@[outclk]() {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": 960, "y1": 450, "x2": 1060, "y2": 550, "rot": 0}
},
"tags": []
}
}
relations
metadata {
"Dyad": {
"icons": {"default": "dyad://DiscreteComponents/Sampler.svg"},
"doc": {"behavior": false}
}
}
endTest Cases ​
No test cases defined.