LIBRARY

Analog.Semiconductors.Tests.PMOSOperatingPoint

Operating-point check for PMOS, the polarity mirror of NMOSOperatingPoint.

Source and bulk sit on a 1.8 V rail and the drain is grounded, so the drain is the lower terminal and uds = -1.8, as MSL's P-channel convention requires. Values from the default MSL card:

beta_eff = Beta*(W + dW)/(L + dL) = 4.711538e-5
ugst     = (Vgate - 1.8 - Vt)*K5 = (Vgate - 0.8)*0.839,  Vt = -1.0

• Vgate = 0 — saturation (uds < ugst < 0), ugst = -0.6712: d.i = -beta_eff*ugst^2/2 + uds*gds = -1.0792963e-5.

• Vgate = 1.6 — cut-off (ugst = +0.6712 >= 0): d.i = uds*gds = -1.8e-7.

The magnitudes are not the NMOS figures scaled: Beta and dL differ, so beta_eff is 3.4x smaller.

Usage

ElectricalComponents.Analog.Semiconductors.Tests.PMOSOperatingPoint(Vgate=0.0)

Parameters:

Name	Description	Units	Default value
Vgate	Gate bias, referred to ground; the rail sits at 1.8 V	V	0.0

Behavior

Source

"""
Operating-point check for PMOS, the polarity mirror of `NMOSOperatingPoint`.

Source and bulk sit on a 1.8 V rail and the drain is grounded, so the drain is the lower
terminal and `uds = -1.8`, as MSL's P-channel convention requires. Values from the
default MSL card:

```
beta_eff = Beta*(W + dW)/(L + dL) = 4.711538e-5
ugst     = (Vgate - 1.8 - Vt)*K5 = (Vgate - 0.8)*0.839,  Vt = -1.0
```

  * `Vgate = 0` — **saturation** (`uds < ugst < 0`), `ugst = -0.6712`:
    `d.i = -beta_eff*ugst^2/2 + uds*gds = -1.0792963e-5`.
  * `Vgate = 1.6` — **cut-off** (`ugst = +0.6712 >= 0`):
    `d.i = uds*gds = -1.8e-7`.

The magnitudes are not the NMOS figures scaled: `Beta` and `dL` differ, so `beta_eff` is
3.4x smaller.
"""
test component PMOSOperatingPoint
  "Supply rail level (1.8 V)"
  supply_lvl = BlockComponents.Sources.Constant(k = 1.8) {
    "Dyad": {"placement": {"diagram": {"x1": 20, "x2": 120, "y1": 120, "y2": 220}}}
  }
  "Supply rail; source and bulk sit on it"
  supply = ElectricalComponents.Analog.Sources.VoltageSource() {
    "Dyad": {"placement": {"diagram": {"x1": 155, "x2": 255, "y1": 225, "y2": 325}}}
  }
  "Gate level"
  gate_sig = BlockComponents.Sources.Constant(k = Vgate) {
    "Dyad": {"placement": {"diagram": {"x1": 150, "x2": 250, "y1": 20, "y2": 120}}}
  }
  "Gate source"
  vg = ElectricalComponents.Analog.Sources.VoltageSource() {
    "Dyad": {"placement": {"diagram": {"x1": 295, "x2": 395, "y1": 330, "y2": 430}}}
  }
  "MOSFET under test, default card"
  m = ElectricalComponents.Analog.Semiconductors.PMOS() {
    "Dyad": {"placement": {"diagram": {"x1": 425, "x2": 525, "y1": 640, "y2": 740}}}
  }
  "Dummy branch resistor; provides a differential state without loading the device"
  r_dummy = ElectricalComponents.Analog.Basic.Resistor(R = 1000) {
    "Dyad": {"placement": {"diagram": {"x1": 565, "x2": 665, "y1": 640, "y2": 740}}}
  }
  "Dummy branch capacitor"
  c_dummy = ElectricalComponents.Analog.Basic.Capacitor(C = 1u) {
    "Dyad": {"placement": {"diagram": {"x1": 695, "x2": 795, "y1": 640, "y2": 740}}}
  }
  "Ground reference"
  ground = ElectricalComponents.Analog.Basic.Ground() {
    "Dyad": {"placement": {"diagram": {"x1": 430, "x2": 530, "y1": 435, "y2": 535}}}
  }
  "Gate bias, referred to ground; the rail sits at 1.8 V"
  parameter Vgate::Voltage = 0.0
relations
  initial c_dummy.v = 0
  connect(supply_lvl.y, supply.V) {"Dyad": {"edges": [{"S": 1, "M": [{"x": 205, "y": 170}], "E": 2}], "path": {}}}
  connect(gate_sig.y, vg.V) {"Dyad": {"edges": [{"S": 1, "M": [{"x": 345, "y": 70}], "E": 2}], "path": {}}}
  connect(supply.p, m.s, m.b, r_dummy.p) {
    "Dyad": {
      "edges": [
        {
          "S": 1,
          "M": [{"x": 140, "y": 275}, {"x": 140, "y": 805}, {"x": 475, "y": 805}],
          "E": 2
        },
        {
          "S": 2,
          "M": [{"x": 475, "y": 755}, {"x": 540, "y": 755}, {"x": 540, "y": 690}],
          "E": 3
        },
        {"S": 3, "M": [], "E": 4}
      ],
      "path": {}
    }
  }
  connect(r_dummy.n, c_dummy.p) {"Dyad": {"edges": [{"S": 1, "M": [], "E": 2}], "path": {}}}
  connect(vg.p, m.g) {
    "Dyad": {
      "edges": [{"S": 1, "M": [{"x": 280, "y": 380}, {"x": 280, "y": 690}], "E": 2}],
      "path": {}
    }
  }
  connect(m.d, c_dummy.n, supply.n, vg.n, ground.g) {
    "Dyad": {
      "edges": [
        {"S": 1, "M": [{"x": 475, "y": 585}, {"x": 810, "y": 585}], "E": -1},
        {"S": -1, "M": [], "E": 2},
        {"S": -1, "M": [{"x": 810, "y": 816}, {"x": 270, "y": 816}], "E": -2},
        {"S": -2, "M": [], "E": 3},
        {"S": -2, "M": [{"x": 410, "y": 275}], "E": -3},
        {"S": -3, "M": [], "E": 4},
        {"S": -3, "M": [{"x": 480, "y": 380}], "E": 5}
      ],
      "junctions": [{"x": 810, "y": 690}, {"x": 270, "y": 275}, {"x": 410, "y": 380}],
      "path": {}
    }
  }
metadata {
  "Dyad": {
    "tests": {
      "case1": {
        "stop": 0.01,
        "atol": {"m.d.i": 1e-10},
        "expect": {"final": {"m.d.i": -0.000010792962769}}
      },
      "case2": {
        "stop": 0.01,
        "params": {"Vgate": 1.6},
        "atol": {"m.d.i": 1e-13},
        "expect": {"final": {"m.d.i": -1.8e-7}}
      }
    }
  }
}
end

Flattened Source

"""
Operating-point check for PMOS, the polarity mirror of `NMOSOperatingPoint`.

Source and bulk sit on a 1.8 V rail and the drain is grounded, so the drain is the lower
terminal and `uds = -1.8`, as MSL's P-channel convention requires. Values from the
default MSL card:

```
beta_eff = Beta*(W + dW)/(L + dL) = 4.711538e-5
ugst     = (Vgate - 1.8 - Vt)*K5 = (Vgate - 0.8)*0.839,  Vt = -1.0
```

  * `Vgate = 0` — **saturation** (`uds < ugst < 0`), `ugst = -0.6712`:
    `d.i = -beta_eff*ugst^2/2 + uds*gds = -1.0792963e-5`.
  * `Vgate = 1.6` — **cut-off** (`ugst = +0.6712 >= 0`):
    `d.i = uds*gds = -1.8e-7`.

The magnitudes are not the NMOS figures scaled: `Beta` and `dL` differ, so `beta_eff` is
3.4x smaller.
"""
test component PMOSOperatingPoint
  "Supply rail level (1.8 V)"
  supply_lvl = BlockComponents.Sources.Constant(k = 1.8) {
    "Dyad": {"placement": {"diagram": {"x1": 20, "x2": 120, "y1": 120, "y2": 220}}}
  }
  "Supply rail; source and bulk sit on it"
  supply = ElectricalComponents.Analog.Sources.VoltageSource() {
    "Dyad": {"placement": {"diagram": {"x1": 155, "x2": 255, "y1": 225, "y2": 325}}}
  }
  "Gate level"
  gate_sig = BlockComponents.Sources.Constant(k = Vgate) {
    "Dyad": {"placement": {"diagram": {"x1": 150, "x2": 250, "y1": 20, "y2": 120}}}
  }
  "Gate source"
  vg = ElectricalComponents.Analog.Sources.VoltageSource() {
    "Dyad": {"placement": {"diagram": {"x1": 295, "x2": 395, "y1": 330, "y2": 430}}}
  }
  "MOSFET under test, default card"
  m = ElectricalComponents.Analog.Semiconductors.PMOS() {
    "Dyad": {"placement": {"diagram": {"x1": 425, "x2": 525, "y1": 640, "y2": 740}}}
  }
  "Dummy branch resistor; provides a differential state without loading the device"
  r_dummy = ElectricalComponents.Analog.Basic.Resistor(R = 1000) {
    "Dyad": {"placement": {"diagram": {"x1": 565, "x2": 665, "y1": 640, "y2": 740}}}
  }
  "Dummy branch capacitor"
  c_dummy = ElectricalComponents.Analog.Basic.Capacitor(C = 1u) {
    "Dyad": {"placement": {"diagram": {"x1": 695, "x2": 795, "y1": 640, "y2": 740}}}
  }
  "Ground reference"
  ground = ElectricalComponents.Analog.Basic.Ground() {
    "Dyad": {"placement": {"diagram": {"x1": 430, "x2": 530, "y1": 435, "y2": 535}}}
  }
  "Gate bias, referred to ground; the rail sits at 1.8 V"
  parameter Vgate::Voltage = 0.0
relations
  initial c_dummy.v = 0
  connect(supply_lvl.y, supply.V) {"Dyad": {"edges": [{"S": 1, "M": [{"x": 205, "y": 170}], "E": 2}], "path": {}}}
  connect(gate_sig.y, vg.V) {"Dyad": {"edges": [{"S": 1, "M": [{"x": 345, "y": 70}], "E": 2}], "path": {}}}
  connect(supply.p, m.s, m.b, r_dummy.p) {
    "Dyad": {
      "edges": [
        {
          "S": 1,
          "M": [{"x": 140, "y": 275}, {"x": 140, "y": 805}, {"x": 475, "y": 805}],
          "E": 2
        },
        {
          "S": 2,
          "M": [{"x": 475, "y": 755}, {"x": 540, "y": 755}, {"x": 540, "y": 690}],
          "E": 3
        },
        {"S": 3, "M": [], "E": 4}
      ],
      "path": {}
    }
  }
  connect(r_dummy.n, c_dummy.p) {"Dyad": {"edges": [{"S": 1, "M": [], "E": 2}], "path": {}}}
  connect(vg.p, m.g) {
    "Dyad": {
      "edges": [{"S": 1, "M": [{"x": 280, "y": 380}, {"x": 280, "y": 690}], "E": 2}],
      "path": {}
    }
  }
  connect(m.d, c_dummy.n, supply.n, vg.n, ground.g) {
    "Dyad": {
      "edges": [
        {"S": 1, "M": [{"x": 475, "y": 585}, {"x": 810, "y": 585}], "E": -1},
        {"S": -1, "M": [], "E": 2},
        {"S": -1, "M": [{"x": 810, "y": 816}, {"x": 270, "y": 816}], "E": -2},
        {"S": -2, "M": [], "E": 3},
        {"S": -2, "M": [{"x": 410, "y": 275}], "E": -3},
        {"S": -3, "M": [], "E": 4},
        {"S": -3, "M": [{"x": 480, "y": 380}], "E": 5}
      ],
      "junctions": [{"x": 810, "y": 690}, {"x": 270, "y": 275}, {"x": 410, "y": 380}],
      "path": {}
    }
  }
metadata {
  "Dyad": {
    "tests": {
      "case1": {
        "stop": 0.01,
        "atol": {"m.d.i": 1e-10},
        "expect": {"final": {"m.d.i": -0.000010792962769}}
      },
      "case2": {
        "stop": 0.01,
        "params": {"Vgate": 1.6},
        "atol": {"m.d.i": 1e-13},
        "expect": {"final": {"m.d.i": -1.8e-7}}
      }
    }
  }
}
end

Test Cases

Test Case case1

Test Case case2

Related

• Examples

• Experiments

• Analyses

• Tests

  • Capacitor

  • Constant

  • Ground

  • PMOS

  • Resistor

  • VoltageSource