LIBRARY
Analog.Semiconductors.Tests.NMOSTest ​
Test circuit for NMOS: a resistively loaded common-source stage under a slow gate ramp.
The gate sweeps 0 to 1.8 V over 1 s with the drain fed from a 1.8 V rail through 1 kOhm, so one run crosses all three regions of the square law. With the default MSL card Vt = 0.8, so the device is in cut-off below Vgate = 0.8 — carrying only the RDS shunt — then saturation, then triode once ugst exceeds uds.
The region seams are C0 but not C1, so m.d.i has visible kinks at them. m.ugst is the K5-scaled gate overdrive that selects the region, so recording it makes the seams legible.
The output capacitor supplies the one differential state; its 1 ms time constant is three decades faster than the ramp, so the curve is the DC characteristic.
Usage ​
ElectricalComponents.Analog.Semiconductors.Tests.NMOSTest()
Behavior ​
Source ​
dyad
"""
Test circuit for NMOS: a resistively loaded common-source stage under a slow gate ramp.
The gate sweeps 0 to 1.8 V over 1 s with the drain fed from a 1.8 V rail through 1 kOhm,
so one run crosses all three regions of the square law. With the default MSL card
`Vt = 0.8`, so the device is in cut-off below `Vgate = 0.8` — carrying only the `RDS`
shunt — then saturation, then triode once `ugst` exceeds `uds`.
The region seams are C0 but not C1, so `m.d.i` has visible kinks at them. `m.ugst` is
the `K5`-scaled gate overdrive that selects the region, so recording it makes the seams
legible.
The output capacitor supplies the one differential state; its 1 ms time constant is
three decades faster than the ramp, so the curve is the DC characteristic.
"""
test component NMOSTest
"Supply rail level (1.8 V)"
supply_lvl = BlockComponents.Sources.Constant(k = 1.8) {
"Dyad": {"placement": {"diagram": {"x1": 20, "y1": 220, "x2": 120, "y2": 320}}}
}
"Supply rail"
supply = ElectricalComponents.Analog.Sources.VoltageSource() {
"Dyad": {"placement": {"diagram": {"x1": 155, "y1": 345, "x2": 255, "y2": 445}}}
}
"Gate ramp: 0 to 1.8 V over 1 s"
gate_sig = BlockComponents.Sources.Ramp(height = 1.8, duration = 1) {
"Dyad": {"placement": {"diagram": {"x1": 150, "y1": 120, "x2": 250, "y2": 220}}}
}
"Gate drive"
gate = ElectricalComponents.Analog.Sources.VoltageSource() {
"Dyad": {"placement": {"diagram": {"x1": 285, "y1": 245, "x2": 385, "y2": 345}}}
}
"Drain load resistor (1 kΩ)"
rd = ElectricalComponents.Analog.Basic.Resistor(R = 1000) {
"Dyad": {"placement": {"diagram": {"x1": 285, "y1": 20, "x2": 385, "y2": 120}}}
}
"MOSFET under test"
m = ElectricalComponents.Analog.Semiconductors.NMOS() {
"Dyad": {"placement": {"diagram": {"x1": 415, "y1": 130, "x2": 515, "y2": 230}}}
}
"Output node capacitance (1 µF); supplies the differential state"
cout = ElectricalComponents.Analog.Basic.Capacitor(C = 1u) {
"Dyad": {"placement": {"diagram": {"x1": 555, "y1": 20, "x2": 655, "y2": 120}}}
}
"Ground reference"
ground = ElectricalComponents.Analog.Basic.Ground() {
"Dyad": {"placement": {"diagram": {"x1": 420, "y1": 350, "x2": 520, "y2": 450}}}
}
relations
"Gate starts at 0, so the device is off and the output sits at the rail"
initial cout.v = 1.8
connect(supply_lvl.y, supply.V) {"Dyad": {"edges": [{"S": 1, "M": [{"x": 205, "y": 270}], "E": 2}], "path": {}}}
connect(gate_sig.y, gate.V) {"Dyad": {"edges": [{"S": 1, "M": [{"x": 335, "y": 170}], "E": 2}], "path": {}}}
connect(supply.p, rd.p) {
"Dyad": {
"edges": [{"S": 1, "M": [{"x": 140, "y": 395}, {"x": 140, "y": 70}], "E": 2}],
"path": {}
}
}
connect(rd.n, m.d, cout.p) {
"Dyad": {
"edges": [
{"S": 1, "M": [], "E": -1},
{"S": -1, "M": [], "E": 2},
{"S": -1, "M": [], "E": 3}
],
"junctions": [{"x": 465, "y": 70}],
"path": {}
}
}
connect(gate.p, m.g) {
"Dyad": {
"edges": [{"S": 1, "M": [{"x": 270, "y": 295}, {"x": 270, "y": 180}], "E": 2}],
"path": {}
}
}
connect(m.s, m.b, cout.n, supply.n, gate.n, ground.g) {
"Dyad": {
"edges": [
{
"S": 1,
"M": [{"x": 465, "y": 245}, {"x": 530, "y": 245}, {"x": 530, "y": 180}],
"E": 2
},
{"S": 2, "M": [], "E": -1},
{"S": -1, "M": [{"x": 670, "y": 70}], "E": 3},
{"S": -1, "M": [{"x": 670, "y": 500}, {"x": 270, "y": 500}], "E": -2},
{"S": -2, "M": [], "E": 4},
{"S": -2, "M": [{"x": 400, "y": 395}], "E": -3},
{"S": -3, "M": [], "E": 5},
{"S": -3, "M": [{"x": 470, "y": 295}], "E": 6}
],
"junctions": [{"x": 670, "y": 180}, {"x": 270, "y": 395}, {"x": 400, "y": 295}],
"path": {}
}
}
metadata {
"Dyad": {
"tests": {"case1": {"stop": 1, "expect": {"signals": ["m.d.i", "m.ugst", "cout.v"]}}}
}
}
endFlattened Source
dyad
"""
Test circuit for NMOS: a resistively loaded common-source stage under a slow gate ramp.
The gate sweeps 0 to 1.8 V over 1 s with the drain fed from a 1.8 V rail through 1 kOhm,
so one run crosses all three regions of the square law. With the default MSL card
`Vt = 0.8`, so the device is in cut-off below `Vgate = 0.8` — carrying only the `RDS`
shunt — then saturation, then triode once `ugst` exceeds `uds`.
The region seams are C0 but not C1, so `m.d.i` has visible kinks at them. `m.ugst` is
the `K5`-scaled gate overdrive that selects the region, so recording it makes the seams
legible.
The output capacitor supplies the one differential state; its 1 ms time constant is
three decades faster than the ramp, so the curve is the DC characteristic.
"""
test component NMOSTest
"Supply rail level (1.8 V)"
supply_lvl = BlockComponents.Sources.Constant(k = 1.8) {
"Dyad": {"placement": {"diagram": {"x1": 20, "y1": 220, "x2": 120, "y2": 320}}}
}
"Supply rail"
supply = ElectricalComponents.Analog.Sources.VoltageSource() {
"Dyad": {"placement": {"diagram": {"x1": 155, "y1": 345, "x2": 255, "y2": 445}}}
}
"Gate ramp: 0 to 1.8 V over 1 s"
gate_sig = BlockComponents.Sources.Ramp(height = 1.8, duration = 1) {
"Dyad": {"placement": {"diagram": {"x1": 150, "y1": 120, "x2": 250, "y2": 220}}}
}
"Gate drive"
gate = ElectricalComponents.Analog.Sources.VoltageSource() {
"Dyad": {"placement": {"diagram": {"x1": 285, "y1": 245, "x2": 385, "y2": 345}}}
}
"Drain load resistor (1 kΩ)"
rd = ElectricalComponents.Analog.Basic.Resistor(R = 1000) {
"Dyad": {"placement": {"diagram": {"x1": 285, "y1": 20, "x2": 385, "y2": 120}}}
}
"MOSFET under test"
m = ElectricalComponents.Analog.Semiconductors.NMOS() {
"Dyad": {"placement": {"diagram": {"x1": 415, "y1": 130, "x2": 515, "y2": 230}}}
}
"Output node capacitance (1 µF); supplies the differential state"
cout = ElectricalComponents.Analog.Basic.Capacitor(C = 1u) {
"Dyad": {"placement": {"diagram": {"x1": 555, "y1": 20, "x2": 655, "y2": 120}}}
}
"Ground reference"
ground = ElectricalComponents.Analog.Basic.Ground() {
"Dyad": {"placement": {"diagram": {"x1": 420, "y1": 350, "x2": 520, "y2": 450}}}
}
relations
"Gate starts at 0, so the device is off and the output sits at the rail"
initial cout.v = 1.8
connect(supply_lvl.y, supply.V) {"Dyad": {"edges": [{"S": 1, "M": [{"x": 205, "y": 270}], "E": 2}], "path": {}}}
connect(gate_sig.y, gate.V) {"Dyad": {"edges": [{"S": 1, "M": [{"x": 335, "y": 170}], "E": 2}], "path": {}}}
connect(supply.p, rd.p) {
"Dyad": {
"edges": [{"S": 1, "M": [{"x": 140, "y": 395}, {"x": 140, "y": 70}], "E": 2}],
"path": {}
}
}
connect(rd.n, m.d, cout.p) {
"Dyad": {
"edges": [
{"S": 1, "M": [], "E": -1},
{"S": -1, "M": [], "E": 2},
{"S": -1, "M": [], "E": 3}
],
"junctions": [{"x": 465, "y": 70}],
"path": {}
}
}
connect(gate.p, m.g) {
"Dyad": {
"edges": [{"S": 1, "M": [{"x": 270, "y": 295}, {"x": 270, "y": 180}], "E": 2}],
"path": {}
}
}
connect(m.s, m.b, cout.n, supply.n, gate.n, ground.g) {
"Dyad": {
"edges": [
{
"S": 1,
"M": [{"x": 465, "y": 245}, {"x": 530, "y": 245}, {"x": 530, "y": 180}],
"E": 2
},
{"S": 2, "M": [], "E": -1},
{"S": -1, "M": [{"x": 670, "y": 70}], "E": 3},
{"S": -1, "M": [{"x": 670, "y": 500}, {"x": 270, "y": 500}], "E": -2},
{"S": -2, "M": [], "E": 4},
{"S": -2, "M": [{"x": 400, "y": 395}], "E": -3},
{"S": -3, "M": [], "E": 5},
{"S": -3, "M": [{"x": 470, "y": 295}], "E": 6}
],
"junctions": [{"x": 670, "y": 180}, {"x": 270, "y": 395}, {"x": 400, "y": 295}],
"path": {}
}
}
metadata {
"Dyad": {
"tests": {"case1": {"stop": 1, "expect": {"signals": ["m.d.i", "m.ugst", "cout.v"]}}}
}
}
endTest Cases ​
Test Case case1 ​
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