LIBRARY

`Analog.Semiconductors.PMOS`

P-channel MOSFET with a heat port, translated from MSL. The mirror of NMOS: same square law with every comparison reversed and the channel terms negated.

Signs

Vt is negative here, -1.0 V by default, as in MSL. kvt is negative too. ud is the lower of the drain and source potentials and us the higher, so uds <= 0.

Temperature

Identical in form to NMOS, and inert at T = Tnom:

Modes

Both flags default to false, which reproduces MSL. use_heat_port couples port; otherwise the device sits at T. MSL ties the two together through ConditionalHeatPort(useHeatPort = useTemperatureDependency), so set both true for a heated device.

Connectors

d drain, g gate, s source, b bulk
port heat port, active when use_heat_port = true

Reference

Modelica.Electrical.Analog.Semiconductors.PMOS, Modelica Standard Library. Parameter names and defaults are MSL's, verbatim.

Usage

ElectricalComponents.Analog.Semiconductors.PMOS(W=20.0e-6, L=6.0e-6, Beta=0.0105e-3, Vt=-1.0, K2=0.41, K5=0.839, dW=-2.5e-6, dL=-2.1e-6, RDS=1.0e7, Tnom=300.15, kvt=-2.9e-3, kk2=6.2e-4, T=293.15, gds=ifelse(abs(RDS) < 1.0e-20, 1.0e20, 1.0 / RDS))

Parameters:

Name	Description	Units	Default value
`use_heat_port`	Couple to `port`; when false the device sits at `T` and `port` must be left unconnected	–	false
`use_temperature_dependency`	Scale `Beta`, `Vt` and `K2` with temperature, MSL `useTemperatureDependency`	–	false
`W`	Channel width	m	20.0e-6
`L`	Channel length	m	6.0e-6
`Beta`	Transconductance parameter	A/V2	0.0105e-3
`Vt`	Zero-bias threshold voltage; negative for a P-channel device, as in MSL	V	-1.0
`K2`	Bulk threshold (body-effect) parameter	–	0.41
`K5`	Reduction of the pinch-off region	–	0.839
`dW`	Narrowing of the channel	m	-2.5e-6
`dL`	Shortening of the channel	m	-2.1e-6
`RDS`	Drain-source resistance, shunting the channel in every region	Ω	1.0e7
`Tnom`	Reference temperature at which `Beta`, `Vt` and `K2` are quoted	K	300.15
`kvt`	Fitting parameter for the `Vt` temperature drift	–	-2.9e-3
`kk2`	Fitting parameter for the `K2` temperature drift	–	6.2e-4
`T`	Fixed device temperature, used when `use_heat_port = false`	K	293.15

Connectors

d - This connector represents an electrical pin with voltage and current as the potential and flow variables, respectively. (Pin)
g - This connector represents an electrical pin with voltage and current as the potential and flow variables, respectively. (Pin)
s - This connector represents an electrical pin with voltage and current as the potential and flow variables, respectively. (Pin)
b - This connector represents an electrical pin with voltage and current as the potential and flow variables, respectively. (Pin)
port - This connector represents a thermal port with temperature and heat flow as the potential and flow variables, respectively. (HeatPort)

Variables

Name	Description	Units
`T_dev`	Device temperature	K
`beta_t`	Transconductance parameter at the device temperature	A/V2
`vt_t`	Threshold voltage at the device temperature	V
`k2_t`	Bulk threshold parameter at the device temperature	–
`beta_eff`	Effective transconductance, `beta_t*(W + dW)/(L + dL)`; MSL calls this bare `v`	A/V2
`ud`	The lower of the drain and source potentials	V
`us`	The higher of the drain and source potentials	V
`uds`	Drain-source voltage after the exchange, never positive	V
`ubs`	Bulk-source voltage, clamped at zero for forward body bias	V
`ugst`	Gate overdrive, scaled by `K5`	V
`id`	Channel current, in the exchanged frame	A
`LossPower`	Power dissipated in the device	W

Behavior

Source

dyad

"""
P-channel MOSFET with a heat port, translated from MSL. The mirror of `NMOS`: same
square law with every comparison reversed and the channel terms negated.

```math
u_{gst} = (v_G - u_S - V_t + K_2 u_{bs})\, K_5, \qquad
\beta_{eff} = \beta \frac{W + dW}{L + dL}
```
```math
i_d = \begin{cases}
  u_{ds} g_{ds}                                            & u_{gst} \ge 0 \\
  -\beta_{eff} u_{ds} (u_{gst} - u_{ds}/2) + u_{ds} g_{ds}  & u_{gst} < u_{ds} \\
  -\beta_{eff} u_{gst}^2 / 2 + u_{ds} g_{ds}                & \text{otherwise}
\end{cases}
```

## Signs

**`Vt` is negative here**, `-1.0` V by default, as in MSL. `kvt` is negative too. `ud`
is the *lower* of the drain and source potentials and `us` the higher, so `uds <= 0`.

## Temperature

Identical in form to `NMOS`, and inert at `T = Tnom`:
```math
\beta(T) = \beta \left(\frac{T}{T_{nom}}\right)^{-1.5}, \quad
V_t(T) = V_t (1 + (T - T_{nom}) k_{vt}), \quad
K_2(T) = K_2 (1 + (T - T_{nom}) k_{k2})
```

## Modes

**Both flags default to `false`, which reproduces MSL.** `use_heat_port` couples `port`;
otherwise the device sits at `T`. MSL ties the two together through
`ConditionalHeatPort(useHeatPort = useTemperatureDependency)`, so set both true for a
heated device.

## Connectors

  * `d` drain, `g` gate, `s` source, `b` bulk
  * `port` heat port, active when `use_heat_port = true`

## Reference

`Modelica.Electrical.Analog.Semiconductors.PMOS`, Modelica Standard Library. Parameter
names and defaults are MSL's, verbatim.
"""
component PMOS
  "Drain pin"
  d = Pin() {"Dyad": {"placement": {"icon": {"x1": 450, "y1": -50, "x2": 550, "y2": 50}}}}
  "Gate pin"
  g = Pin() {"Dyad": {"placement": {"icon": {"x1": -50, "y1": 450, "x2": 50, "y2": 550}}}}
  "Source pin"
  s = Pin() {"Dyad": {"placement": {"icon": {"x1": 450, "y1": 950, "x2": 550, "y2": 1050}}}}
  "Bulk (substrate) pin"
  b = Pin() {"Dyad": {"placement": {"icon": {"x1": 950, "y1": 450, "x2": 1050, "y2": 550}}}}
  "Heat port for thermal-electric simulation"
  port = HeatPort() {"Dyad": {"placement": {"icon": {"x1": -50, "y1": 750, "x2": 50, "y2": 850}}}}
  "Couple to `port`; when false the device sits at `T` and `port` must be left unconnected"
  structural parameter use_heat_port::Boolean = false
  "Scale `Beta`, `Vt` and `K2` with temperature, MSL `useTemperatureDependency`"
  structural parameter use_temperature_dependency::Boolean = false
  "Channel width"
  parameter W::Length = 20.0e-6
  "Channel length"
  parameter L::Length = 6.0e-6
  "Transconductance parameter"
  parameter Beta::Transconductance = 0.0105e-3
  "Zero-bias threshold voltage; negative for a P-channel device, as in MSL"
  parameter Vt::Voltage = -1.0
  "Bulk threshold (body-effect) parameter"
  parameter K2::Real = 0.41
  "Reduction of the pinch-off region"
  parameter K5::Real = 0.839
  "Narrowing of the channel"
  parameter dW::Length = -2.5e-6
  "Shortening of the channel"
  parameter dL::Length = -2.1e-6
  "Drain-source resistance, shunting the channel in every region"
  parameter RDS::Resistance = 1.0e7
  "Reference temperature at which `Beta`, `Vt` and `K2` are quoted"
  parameter Tnom::Temperature = 300.15
  "Fitting parameter for the `Vt` temperature drift"
  parameter kvt::Real = -2.9e-3
  "Fitting parameter for the `K2` temperature drift"
  parameter kk2::Real = 6.2e-4
  "Fixed device temperature, used when `use_heat_port = false`"
  parameter T::Temperature = 293.15
  "Drain-source conductance, `1/RDS`, clamped for a vanishing `RDS`"
  final parameter gds::Conductance = ifelse(abs(RDS) < 1.0e-20, 1.0e20, 1.0 / RDS)
  "Device temperature"
  variable T_dev::Temperature
  "Transconductance parameter at the device temperature"
  variable beta_t::Transconductance
  "Threshold voltage at the device temperature"
  variable vt_t::Voltage
  "Bulk threshold parameter at the device temperature"
  variable k2_t::Real
  "Effective transconductance, `beta_t*(W + dW)/(L + dL)`; MSL calls this bare `v`"
  variable beta_eff::Transconductance
  "The lower of the drain and source potentials"
  variable ud::Voltage
  "The higher of the drain and source potentials"
  variable us::Voltage
  "Drain-source voltage after the exchange, never positive"
  variable uds::Voltage
  "Bulk-source voltage, clamped at zero for forward body bias"
  variable ubs::Voltage
  "Gate overdrive, scaled by `K5`"
  variable ugst::Voltage
  "Channel current, in the exchanged frame"
  variable id::Current
  "Power dissipated in the device"
  variable LossPower::Power
relations
  assert(L + dL > 0.0, "PMOS: effective length must be positive")
  assert(W + dW > 0.0, "PMOS: effective width must be positive")
  assert(T_dev > 0.0, "PMOS: device temperature must be positive")
  if use_heat_port
    T_dev = port.T
    port.Q_flow = -LossPower
  else
    T_dev = T
    port.T = T
    port.Q_flow = 0
  end
  if use_temperature_dependency
    beta_t = Beta * (T_dev / Tnom) ^ (-1.5)
    vt_t = Vt * (1.0 + (T_dev - Tnom) * kvt)
    k2_t = K2 * (1.0 + (T_dev - Tnom) * kk2)
  else
    beta_t = Beta
    vt_t = Vt
    k2_t = K2
  end
  beta_eff = beta_t * (W + dW) / (L + dL)
  "Drain-source exchange, reversed for the P-channel, so `uds <= 0`"
  ud = ifelse(d.v > s.v, s.v, d.v)
  us = ifelse(d.v > s.v, d.v, s.v)
  uds = ud - us
  "Forward body bias is clamped away, as in MSL"
  ubs = ifelse(b.v < us, 0.0, b.v - us)
  ugst = (g.v - us - vt_t + k2_t * ubs) * K5
  """
  Cut-off, triode and saturation, with the channel terms negated. Above threshold the
  current is the `RDS` shunt alone, so the device is exactly off.
  """
  id = ifelse(ugst >= 0.0, uds * gds, ifelse(ugst < uds, -beta_eff * uds * (ugst - uds / 2.0) + uds * gds, -beta_eff * ugst * ugst / 2.0 + uds * gds))
  g.i = 0
  d.i = ifelse(d.v > s.v, -id, id)
  s.i = ifelse(d.v > s.v, id, -id)
  b.i = 0
  LossPower = d.i * (d.v - s.v)
metadata {
  "Dyad": {
    "labels": [{"label": "$(instance)", "x": 500, "y": 1200, "rot": 0}],
    "icons": {"default": "dyad://ElectricalComponents/PMOS.svg"}
  }
}
end

Flattened Source

dyad

"""
P-channel MOSFET with a heat port, translated from MSL. The mirror of `NMOS`: same
square law with every comparison reversed and the channel terms negated.

```math
u_{gst} = (v_G - u_S - V_t + K_2 u_{bs})\, K_5, \qquad
\beta_{eff} = \beta \frac{W + dW}{L + dL}
```
```math
i_d = \begin{cases}
  u_{ds} g_{ds}                                            & u_{gst} \ge 0 \\
  -\beta_{eff} u_{ds} (u_{gst} - u_{ds}/2) + u_{ds} g_{ds}  & u_{gst} < u_{ds} \\
  -\beta_{eff} u_{gst}^2 / 2 + u_{ds} g_{ds}                & \text{otherwise}
\end{cases}
```

## Signs

**`Vt` is negative here**, `-1.0` V by default, as in MSL. `kvt` is negative too. `ud`
is the *lower* of the drain and source potentials and `us` the higher, so `uds <= 0`.

## Temperature

Identical in form to `NMOS`, and inert at `T = Tnom`:
```math
\beta(T) = \beta \left(\frac{T}{T_{nom}}\right)^{-1.5}, \quad
V_t(T) = V_t (1 + (T - T_{nom}) k_{vt}), \quad
K_2(T) = K_2 (1 + (T - T_{nom}) k_{k2})
```

## Modes

**Both flags default to `false`, which reproduces MSL.** `use_heat_port` couples `port`;
otherwise the device sits at `T`. MSL ties the two together through
`ConditionalHeatPort(useHeatPort = useTemperatureDependency)`, so set both true for a
heated device.

## Connectors

  * `d` drain, `g` gate, `s` source, `b` bulk
  * `port` heat port, active when `use_heat_port = true`

## Reference

`Modelica.Electrical.Analog.Semiconductors.PMOS`, Modelica Standard Library. Parameter
names and defaults are MSL's, verbatim.
"""
component PMOS
  "Drain pin"
  d = Pin() {"Dyad": {"placement": {"icon": {"x1": 450, "y1": -50, "x2": 550, "y2": 50}}}}
  "Gate pin"
  g = Pin() {"Dyad": {"placement": {"icon": {"x1": -50, "y1": 450, "x2": 50, "y2": 550}}}}
  "Source pin"
  s = Pin() {"Dyad": {"placement": {"icon": {"x1": 450, "y1": 950, "x2": 550, "y2": 1050}}}}
  "Bulk (substrate) pin"
  b = Pin() {"Dyad": {"placement": {"icon": {"x1": 950, "y1": 450, "x2": 1050, "y2": 550}}}}
  "Heat port for thermal-electric simulation"
  port = HeatPort() {"Dyad": {"placement": {"icon": {"x1": -50, "y1": 750, "x2": 50, "y2": 850}}}}
  "Couple to `port`; when false the device sits at `T` and `port` must be left unconnected"
  structural parameter use_heat_port::Boolean = false
  "Scale `Beta`, `Vt` and `K2` with temperature, MSL `useTemperatureDependency`"
  structural parameter use_temperature_dependency::Boolean = false
  "Channel width"
  parameter W::Length = 20.0e-6
  "Channel length"
  parameter L::Length = 6.0e-6
  "Transconductance parameter"
  parameter Beta::Transconductance = 0.0105e-3
  "Zero-bias threshold voltage; negative for a P-channel device, as in MSL"
  parameter Vt::Voltage = -1.0
  "Bulk threshold (body-effect) parameter"
  parameter K2::Real = 0.41
  "Reduction of the pinch-off region"
  parameter K5::Real = 0.839
  "Narrowing of the channel"
  parameter dW::Length = -2.5e-6
  "Shortening of the channel"
  parameter dL::Length = -2.1e-6
  "Drain-source resistance, shunting the channel in every region"
  parameter RDS::Resistance = 1.0e7
  "Reference temperature at which `Beta`, `Vt` and `K2` are quoted"
  parameter Tnom::Temperature = 300.15
  "Fitting parameter for the `Vt` temperature drift"
  parameter kvt::Real = -2.9e-3
  "Fitting parameter for the `K2` temperature drift"
  parameter kk2::Real = 6.2e-4
  "Fixed device temperature, used when `use_heat_port = false`"
  parameter T::Temperature = 293.15
  "Drain-source conductance, `1/RDS`, clamped for a vanishing `RDS`"
  final parameter gds::Conductance = ifelse(abs(RDS) < 1.0e-20, 1.0e20, 1.0 / RDS)
  "Device temperature"
  variable T_dev::Temperature
  "Transconductance parameter at the device temperature"
  variable beta_t::Transconductance
  "Threshold voltage at the device temperature"
  variable vt_t::Voltage
  "Bulk threshold parameter at the device temperature"
  variable k2_t::Real
  "Effective transconductance, `beta_t*(W + dW)/(L + dL)`; MSL calls this bare `v`"
  variable beta_eff::Transconductance
  "The lower of the drain and source potentials"
  variable ud::Voltage
  "The higher of the drain and source potentials"
  variable us::Voltage
  "Drain-source voltage after the exchange, never positive"
  variable uds::Voltage
  "Bulk-source voltage, clamped at zero for forward body bias"
  variable ubs::Voltage
  "Gate overdrive, scaled by `K5`"
  variable ugst::Voltage
  "Channel current, in the exchanged frame"
  variable id::Current
  "Power dissipated in the device"
  variable LossPower::Power
relations
  assert(L + dL > 0.0, "PMOS: effective length must be positive")
  assert(W + dW > 0.0, "PMOS: effective width must be positive")
  assert(T_dev > 0.0, "PMOS: device temperature must be positive")
  if use_heat_port
    T_dev = port.T
    port.Q_flow = -LossPower
  else
    T_dev = T
    port.T = T
    port.Q_flow = 0
  end
  if use_temperature_dependency
    beta_t = Beta * (T_dev / Tnom) ^ (-1.5)
    vt_t = Vt * (1.0 + (T_dev - Tnom) * kvt)
    k2_t = K2 * (1.0 + (T_dev - Tnom) * kk2)
  else
    beta_t = Beta
    vt_t = Vt
    k2_t = K2
  end
  beta_eff = beta_t * (W + dW) / (L + dL)
  "Drain-source exchange, reversed for the P-channel, so `uds <= 0`"
  ud = ifelse(d.v > s.v, s.v, d.v)
  us = ifelse(d.v > s.v, d.v, s.v)
  uds = ud - us
  "Forward body bias is clamped away, as in MSL"
  ubs = ifelse(b.v < us, 0.0, b.v - us)
  ugst = (g.v - us - vt_t + k2_t * ubs) * K5
  """
  Cut-off, triode and saturation, with the channel terms negated. Above threshold the
  current is the `RDS` shunt alone, so the device is exactly off.
  """
  id = ifelse(ugst >= 0.0, uds * gds, ifelse(ugst < uds, -beta_eff * uds * (ugst - uds / 2.0) + uds * gds, -beta_eff * ugst * ugst / 2.0 + uds * gds))
  g.i = 0
  d.i = ifelse(d.v > s.v, -id, id)
  s.i = ifelse(d.v > s.v, id, -id)
  b.i = 0
  LossPower = d.i * (d.v - s.v)
metadata {
  "Dyad": {
    "labels": [{"label": "$(instance)", "x": 500, "y": 1200, "rot": 0}],
    "icons": {"default": "dyad://ElectricalComponents/PMOS.svg"}
  }
}
end

Test Cases

No test cases defined.

Examples
Experiments
Analyses
Tests
- PMOSOperatingPoint
- PMOSTest

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Analog.Semiconductors.PMOS ​

Signs ​

Temperature ​

Modes ​

Connectors ​

Reference ​

Usage ​

Parameters: ​

Connectors ​

Variables ​

Behavior ​

Source ​

Test Cases ​

Related ​

`Analog.Semiconductors.PMOS`

Signs

Temperature

Modes

Connectors

Reference

Usage

Parameters:

Connectors

Variables

Behavior

Source

Test Cases

Related