LIBRARY

Analog.Semiconductors.Tests.NMOSOperatingPoint

Operating-point check for NMOS, one case per region of the square law.

All four terminals are driven. Values from the MSL square law at the default MSL card, drain at 1.8 V, source and bulk grounded:

beta_eff = Beta*(W + dW)/(L + dL) = 1.594444e-4
ugst     = (Vgate - Vt)*K5,  Vt = 0.8, K5 = 0.7311
gds      = 1/RDS = 1e-7

• Vgate = 1.8 — saturation (0 < ugst < uds), ugst = 0.7311: d.i = beta_eff*ugst^2/2 + uds*gds = 4.279210e-5.

• Vgate = 0.2 — cut-off (ugst = -0.43866 <= 0): d.i = uds*gds = 1.8e-7, the RDS shunt alone.

The second case is the point of the test: below threshold the square law is exactly off. There is no subthreshold exponential.

The dummy RC branch supplies the one differential state a transient test needs.

Usage

ElectricalComponents.Analog.Semiconductors.Tests.NMOSOperatingPoint(Vgate=1.8, Vdrain=1.8)

Parameters:

Name	Description	Units	Default value
Vgate	Gate bias	V	1.8
Vdrain	Drain bias	V	1.8

Behavior

Source

"""
Operating-point check for NMOS, one case per region of the square law.

All four terminals are driven. Values from the MSL square law at the default MSL card,
drain at 1.8 V, source and bulk grounded:

```
beta_eff = Beta*(W + dW)/(L + dL) = 1.594444e-4
ugst     = (Vgate - Vt)*K5,  Vt = 0.8, K5 = 0.7311
gds      = 1/RDS = 1e-7
```

  * `Vgate = 1.8` — **saturation** (`0 < ugst < uds`), `ugst = 0.7311`:
    `d.i = beta_eff*ugst^2/2 + uds*gds = 4.279210e-5`.
  * `Vgate = 0.2` — **cut-off** (`ugst = -0.43866 <= 0`):
    `d.i = uds*gds = 1.8e-7`, the `RDS` shunt alone.

The second case is the point of the test: below threshold the square law is exactly off.
There is no subthreshold exponential.

The dummy RC branch supplies the one differential state a transient test needs.
"""
test component NMOSOperatingPoint
  "Gate level"
  gate_sig = BlockComponents.Sources.Constant(k = Vgate) {
    "Dyad": {"placement": {"diagram": {"x1": 20, "x2": 120, "y1": 120, "y2": 220}}}
  }
  "Gate source"
  vg = ElectricalComponents.Analog.Sources.VoltageSource() {
    "Dyad": {"placement": {"diagram": {"x1": 155, "x2": 255, "y1": 225, "y2": 325}}}
  }
  "Drain level"
  drain_sig = BlockComponents.Sources.Constant(k = Vdrain) {
    "Dyad": {"placement": {"diagram": {"x1": 150, "x2": 250, "y1": 20, "y2": 120}}}
  }
  "Drain source"
  vd = ElectricalComponents.Analog.Sources.VoltageSource() {
    "Dyad": {"placement": {"diagram": {"x1": 295, "x2": 395, "y1": 125, "y2": 225}}}
  }
  "MOSFET under test, default card"
  m = ElectricalComponents.Analog.Semiconductors.NMOS() {
    "Dyad": {"placement": {"diagram": {"x1": 425, "x2": 525, "y1": 445, "y2": 545}}}
  }
  "Dummy branch resistor; provides a differential state without loading the device"
  r_dummy = ElectricalComponents.Analog.Basic.Resistor(R = 1000) {
    "Dyad": {"placement": {"diagram": {"x1": 565, "x2": 665, "y1": 340, "y2": 440}}}
  }
  "Dummy branch capacitor"
  c_dummy = ElectricalComponents.Analog.Basic.Capacitor(C = 1u) {
    "Dyad": {"placement": {"diagram": {"x1": 695, "x2": 795, "y1": 340, "y2": 440}}}
  }
  "Ground reference"
  ground = ElectricalComponents.Analog.Basic.Ground() {
    "Dyad": {"placement": {"diagram": {"x1": 430, "x2": 530, "y1": 230, "y2": 330}}}
  }
  "Gate bias"
  parameter Vgate::Voltage = 1.8
  "Drain bias"
  parameter Vdrain::Voltage = 1.8
relations
  initial c_dummy.v = 0
  connect(gate_sig.y, vg.V) {"Dyad": {"edges": [{"S": 1, "M": [{"x": 205, "y": 170}], "E": 2}], "path": {}}}
  connect(drain_sig.y, vd.V) {"Dyad": {"edges": [{"S": 1, "M": [{"x": 345, "y": 70}], "E": 2}], "path": {}}}
  connect(vg.p, m.g, r_dummy.p) {
    "Dyad": {
      "edges": [
        {"S": 1, "M": [{"x": 140, "y": 275}, {"x": 140, "y": 495}], "E": -1},
        {"S": -1, "M": [], "E": 2},
        {"S": -1, "M": [{"x": 410, "y": 390}], "E": 3}
      ],
      "junctions": [{"x": 410, "y": 495}],
      "path": {}
    }
  }
  connect(r_dummy.n, c_dummy.p) {"Dyad": {"edges": [{"S": 1, "M": [], "E": 2}], "path": {}}}
  connect(vd.p, m.d) {
    "Dyad": {
      "edges": [
        {
          "S": 1,
          "M": [{"x": 280, "y": 175}, {"x": 280, "y": 380}, {"x": 475, "y": 380}],
          "E": 2
        }
      ],
      "path": {}
    }
  }
  connect(m.s, m.b, c_dummy.n, vg.n, vd.n, ground.g) {
    "Dyad": {
      "edges": [
        {
          "S": 1,
          "M": [{"x": 475, "y": 560}, {"x": 540, "y": 560}, {"x": 540, "y": 495}],
          "E": 2
        },
        {"S": 2, "M": [], "E": -1},
        {"S": -1, "M": [{"x": 810, "y": 390}], "E": 3},
        {"S": -1, "M": [{"x": 810, "y": 610}, {"x": 270, "y": 610}], "E": -2},
        {"S": -2, "M": [], "E": 4},
        {"S": -2, "M": [{"x": 410, "y": 275}], "E": -3},
        {"S": -3, "M": [], "E": 5},
        {"S": -3, "M": [{"x": 480, "y": 175}], "E": 6}
      ],
      "junctions": [{"x": 810, "y": 495}, {"x": 270, "y": 275}, {"x": 410, "y": 175}],
      "path": {}
    }
  }
metadata {
  "Dyad": {
    "tests": {
      "case1": {
        "stop": 0.01,
        "atol": {"m.d.i": 1e-10},
        "expect": {"final": {"m.d.i": 0.000042792102575}}
      },
      "case2": {
        "stop": 0.01,
        "params": {"Vgate": 0.2},
        "atol": {"m.d.i": 1e-13},
        "expect": {"final": {"m.d.i": 1.8e-7}}
      }
    }
  }
}
end

Flattened Source

"""
Operating-point check for NMOS, one case per region of the square law.

All four terminals are driven. Values from the MSL square law at the default MSL card,
drain at 1.8 V, source and bulk grounded:

```
beta_eff = Beta*(W + dW)/(L + dL) = 1.594444e-4
ugst     = (Vgate - Vt)*K5,  Vt = 0.8, K5 = 0.7311
gds      = 1/RDS = 1e-7
```

  * `Vgate = 1.8` — **saturation** (`0 < ugst < uds`), `ugst = 0.7311`:
    `d.i = beta_eff*ugst^2/2 + uds*gds = 4.279210e-5`.
  * `Vgate = 0.2` — **cut-off** (`ugst = -0.43866 <= 0`):
    `d.i = uds*gds = 1.8e-7`, the `RDS` shunt alone.

The second case is the point of the test: below threshold the square law is exactly off.
There is no subthreshold exponential.

The dummy RC branch supplies the one differential state a transient test needs.
"""
test component NMOSOperatingPoint
  "Gate level"
  gate_sig = BlockComponents.Sources.Constant(k = Vgate) {
    "Dyad": {"placement": {"diagram": {"x1": 20, "x2": 120, "y1": 120, "y2": 220}}}
  }
  "Gate source"
  vg = ElectricalComponents.Analog.Sources.VoltageSource() {
    "Dyad": {"placement": {"diagram": {"x1": 155, "x2": 255, "y1": 225, "y2": 325}}}
  }
  "Drain level"
  drain_sig = BlockComponents.Sources.Constant(k = Vdrain) {
    "Dyad": {"placement": {"diagram": {"x1": 150, "x2": 250, "y1": 20, "y2": 120}}}
  }
  "Drain source"
  vd = ElectricalComponents.Analog.Sources.VoltageSource() {
    "Dyad": {"placement": {"diagram": {"x1": 295, "x2": 395, "y1": 125, "y2": 225}}}
  }
  "MOSFET under test, default card"
  m = ElectricalComponents.Analog.Semiconductors.NMOS() {
    "Dyad": {"placement": {"diagram": {"x1": 425, "x2": 525, "y1": 445, "y2": 545}}}
  }
  "Dummy branch resistor; provides a differential state without loading the device"
  r_dummy = ElectricalComponents.Analog.Basic.Resistor(R = 1000) {
    "Dyad": {"placement": {"diagram": {"x1": 565, "x2": 665, "y1": 340, "y2": 440}}}
  }
  "Dummy branch capacitor"
  c_dummy = ElectricalComponents.Analog.Basic.Capacitor(C = 1u) {
    "Dyad": {"placement": {"diagram": {"x1": 695, "x2": 795, "y1": 340, "y2": 440}}}
  }
  "Ground reference"
  ground = ElectricalComponents.Analog.Basic.Ground() {
    "Dyad": {"placement": {"diagram": {"x1": 430, "x2": 530, "y1": 230, "y2": 330}}}
  }
  "Gate bias"
  parameter Vgate::Voltage = 1.8
  "Drain bias"
  parameter Vdrain::Voltage = 1.8
relations
  initial c_dummy.v = 0
  connect(gate_sig.y, vg.V) {"Dyad": {"edges": [{"S": 1, "M": [{"x": 205, "y": 170}], "E": 2}], "path": {}}}
  connect(drain_sig.y, vd.V) {"Dyad": {"edges": [{"S": 1, "M": [{"x": 345, "y": 70}], "E": 2}], "path": {}}}
  connect(vg.p, m.g, r_dummy.p) {
    "Dyad": {
      "edges": [
        {"S": 1, "M": [{"x": 140, "y": 275}, {"x": 140, "y": 495}], "E": -1},
        {"S": -1, "M": [], "E": 2},
        {"S": -1, "M": [{"x": 410, "y": 390}], "E": 3}
      ],
      "junctions": [{"x": 410, "y": 495}],
      "path": {}
    }
  }
  connect(r_dummy.n, c_dummy.p) {"Dyad": {"edges": [{"S": 1, "M": [], "E": 2}], "path": {}}}
  connect(vd.p, m.d) {
    "Dyad": {
      "edges": [
        {
          "S": 1,
          "M": [{"x": 280, "y": 175}, {"x": 280, "y": 380}, {"x": 475, "y": 380}],
          "E": 2
        }
      ],
      "path": {}
    }
  }
  connect(m.s, m.b, c_dummy.n, vg.n, vd.n, ground.g) {
    "Dyad": {
      "edges": [
        {
          "S": 1,
          "M": [{"x": 475, "y": 560}, {"x": 540, "y": 560}, {"x": 540, "y": 495}],
          "E": 2
        },
        {"S": 2, "M": [], "E": -1},
        {"S": -1, "M": [{"x": 810, "y": 390}], "E": 3},
        {"S": -1, "M": [{"x": 810, "y": 610}, {"x": 270, "y": 610}], "E": -2},
        {"S": -2, "M": [], "E": 4},
        {"S": -2, "M": [{"x": 410, "y": 275}], "E": -3},
        {"S": -3, "M": [], "E": 5},
        {"S": -3, "M": [{"x": 480, "y": 175}], "E": 6}
      ],
      "junctions": [{"x": 810, "y": 495}, {"x": 270, "y": 275}, {"x": 410, "y": 175}],
      "path": {}
    }
  }
metadata {
  "Dyad": {
    "tests": {
      "case1": {
        "stop": 0.01,
        "atol": {"m.d.i": 1e-10},
        "expect": {"final": {"m.d.i": 0.000042792102575}}
      },
      "case2": {
        "stop": 0.01,
        "params": {"Vgate": 0.2},
        "atol": {"m.d.i": 1e-13},
        "expect": {"final": {"m.d.i": 1.8e-7}}
      }
    }
  }
}
end

Test Cases

Test Case case1

Test Case case2

Related

• Examples

• Experiments

• Analyses

• Tests

  • Capacitor

  • Constant

  • Ground

  • NMOS

  • Resistor

  • VoltageSource