LIBRARY
Analog.Basic.Tests.VCV
Test circuit for VCV (voltage-controlled voltage source).
A sine voltage source (amplitude=1 V, frequency=1 Hz) drives the VCV input port (port 1). A 10 Ω resistor loads the output port (port 2). VCV gain = 2.
Expected (algebraic, holds for all t):
v1 = sin(2π·t)
v2 = gain·v1 = 2·sin(2π·t)
i1 = 0 (infinite input impedance)
i2 = −v2/R_load = −0.2·sin(2π·t)
Usage
ElectricalComponents.Analog.Basic.Tests.VCV()
Behavior
julia
using ElectricalComponents #hide
using ModelingToolkit #hide
@named sys = ElectricalComponents.Analog.Basic.Tests.VCV() #hide
full_equations(sys) #hide<< @example-block not executed in draft mode >>Source
dyad
"""
Test circuit for VCV (voltage-controlled voltage source).
A sine voltage source (amplitude=1 V, frequency=1 Hz) drives the VCV input
port (port 1). A 10 Ω resistor loads the output port (port 2).
VCV gain = 2.
Expected (algebraic, holds for all t):
- v1 = sin(2π·t)
- v2 = gain·v1 = 2·sin(2π·t)
- i1 = 0 (infinite input impedance)
- i2 = −v2/R_load = −0.2·sin(2π·t)
"""
test component VCV
"Sine signal: amplitude=1, frequency=1 Hz"
sine = BlockComponents.Sources.Sine(amplitude = 1, frequency = 1) {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": 0, "y1": 310, "x2": 100, "y2": 410, "rot": 0}
},
"tags": []
}
}
"Input voltage source"
vs = ElectricalComponents.Analog.Sources.VoltageSource() {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": 160, "y1": 410, "x2": 260, "y2": 310, "rot": 90}
},
"tags": []
}
}
"VCV with gain=2"
vcv = ElectricalComponents.Analog.Basic.VCV(gain = 2) {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": 450, "y1": 320, "x2": 550, "y2": 420, "rot": 0}
},
"tags": []
}
}
"Output load resistor"
r_load = ElectricalComponents.Analog.Basic.Resistor(R = 10) {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": 730, "y1": 410, "x2": 830, "y2": 310, "rot": 90}
},
"tags": []
}
}
"Input-side ground"
gnd1 = ElectricalComponents.Analog.Basic.Ground() {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": 160, "y1": 580, "x2": 260, "y2": 680, "rot": 0}
},
"tags": []
}
}
"Output-side ground"
gnd2 = ElectricalComponents.Analog.Basic.Ground() {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": 520, "y1": 580, "x2": 620, "y2": 680, "rot": 0}
},
"tags": []
}
}
relations
connect(sine.y, vs.V) {"Dyad": {"edges": [{"S": 1, "M": [], "E": 2}], "renderStyle": "standard"}}
connect(vs.p, vcv.p1) {
"Dyad": {
"edges": [
{
"S": 1,
"M": [{"x": 210, "y": 250}, {"x": 391, "y": 250}, {"x": 391, "y": 321}],
"E": 2
}
],
"renderStyle": "standard"
}
}
connect(vs.n, gnd1.g) {"Dyad": {"edges": [{"S": 1, "M": [], "E": 2}], "renderStyle": "standard"}}
connect(vs.n, vcv.n1) {
"Dyad": {
"edges": [
{
"S": 1,
"M": [
{"x": 210, "y": 470},
{"x": 390, "y": 470},
{"x": 390, "y": 420},
{"x": 451, "y": 420}
],
"E": 2
}
],
"renderStyle": "standard"
}
}
connect(vcv.p2, r_load.p) {
"Dyad": {
"edges": [{"S": 1, "M": [{"x": 551, "y": 250}, {"x": 780, "y": 250}], "E": 2}],
"renderStyle": "standard"
}
}
connect(r_load.n, vcv.n2) {
"Dyad": {
"edges": [
{
"S": 1,
"M": [{"x": 780, "y": 470}, {"x": 571, "y": 470}, {"x": 571, "y": 420}],
"E": 2
}
],
"renderStyle": "standard"
}
}
connect(vcv.n2, gnd2.g) {
"Dyad": {
"edges": [{"S": 1, "M": [{"x": 570, "y": 420}], "E": 2}],
"renderStyle": "standard"
}
}
metadata {
"Dyad": {
"icons": {"default": "dyad://ElectricalComponents/Example.svg"},
"tests": {
"case1": {"stop": 1, "expect": {"signals": ["vcv.v1", "vcv.v2", "vcv.i1", "vcv.i2"]}}
}
}
}
endFlattened Source
dyad
"""
Test circuit for VCV (voltage-controlled voltage source).
A sine voltage source (amplitude=1 V, frequency=1 Hz) drives the VCV input
port (port 1). A 10 Ω resistor loads the output port (port 2).
VCV gain = 2.
Expected (algebraic, holds for all t):
- v1 = sin(2π·t)
- v2 = gain·v1 = 2·sin(2π·t)
- i1 = 0 (infinite input impedance)
- i2 = −v2/R_load = −0.2·sin(2π·t)
"""
test component VCV
"Sine signal: amplitude=1, frequency=1 Hz"
sine = BlockComponents.Sources.Sine(amplitude = 1, frequency = 1) {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": 0, "y1": 310, "x2": 100, "y2": 410, "rot": 0}
},
"tags": []
}
}
"Input voltage source"
vs = ElectricalComponents.Analog.Sources.VoltageSource() {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": 160, "y1": 410, "x2": 260, "y2": 310, "rot": 90}
},
"tags": []
}
}
"VCV with gain=2"
vcv = ElectricalComponents.Analog.Basic.VCV(gain = 2) {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": 450, "y1": 320, "x2": 550, "y2": 420, "rot": 0}
},
"tags": []
}
}
"Output load resistor"
r_load = ElectricalComponents.Analog.Basic.Resistor(R = 10) {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": 730, "y1": 410, "x2": 830, "y2": 310, "rot": 90}
},
"tags": []
}
}
"Input-side ground"
gnd1 = ElectricalComponents.Analog.Basic.Ground() {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": 160, "y1": 580, "x2": 260, "y2": 680, "rot": 0}
},
"tags": []
}
}
"Output-side ground"
gnd2 = ElectricalComponents.Analog.Basic.Ground() {
"Dyad": {
"placement": {
"diagram": {"iconName": "default", "x1": 520, "y1": 580, "x2": 620, "y2": 680, "rot": 0}
},
"tags": []
}
}
relations
connect(sine.y, vs.V) {"Dyad": {"edges": [{"S": 1, "M": [], "E": 2}], "renderStyle": "standard"}}
connect(vs.p, vcv.p1) {
"Dyad": {
"edges": [
{
"S": 1,
"M": [{"x": 210, "y": 250}, {"x": 391, "y": 250}, {"x": 391, "y": 321}],
"E": 2
}
],
"renderStyle": "standard"
}
}
connect(vs.n, gnd1.g) {"Dyad": {"edges": [{"S": 1, "M": [], "E": 2}], "renderStyle": "standard"}}
connect(vs.n, vcv.n1) {
"Dyad": {
"edges": [
{
"S": 1,
"M": [
{"x": 210, "y": 470},
{"x": 390, "y": 470},
{"x": 390, "y": 420},
{"x": 451, "y": 420}
],
"E": 2
}
],
"renderStyle": "standard"
}
}
connect(vcv.p2, r_load.p) {
"Dyad": {
"edges": [{"S": 1, "M": [{"x": 551, "y": 250}, {"x": 780, "y": 250}], "E": 2}],
"renderStyle": "standard"
}
}
connect(r_load.n, vcv.n2) {
"Dyad": {
"edges": [
{
"S": 1,
"M": [{"x": 780, "y": 470}, {"x": 571, "y": 470}, {"x": 571, "y": 420}],
"E": 2
}
],
"renderStyle": "standard"
}
}
connect(vcv.n2, gnd2.g) {
"Dyad": {
"edges": [{"S": 1, "M": [{"x": 570, "y": 420}], "E": 2}],
"renderStyle": "standard"
}
}
metadata {
"Dyad": {
"icons": {"default": "dyad://ElectricalComponents/Example.svg"},
"tests": {
"case1": {"stop": 1, "expect": {"signals": ["vcv.v1", "vcv.v2", "vcv.i1", "vcv.i2"]}}
}
}
}
endTest Cases
julia
using ElectricalComponents
using DyadInterface: TransientAnalysis, rebuild_sol, ODEAlg
using ModelingToolkit: toggle_namespacing, get_initial_conditions, @named
using CSV, DataFrames, Plots
snapshotsdir = joinpath(dirname(dirname(pathof(ElectricalComponents))), "test", "snapshots")<< @setup-block not executed in draft mode >>Test Case case1
julia
@named model_case1 = ElectricalComponents.Analog.Basic.Tests.VCV()
model_case1 = toggle_namespacing(model_case1, false)
model_case1 = toggle_namespacing(model_case1, true)
result_case1 = TransientAnalysis(; model = model_case1, alg = ODEAlg.Auto(), start = 0e+0, stop = 1e+0, abstol=1e-6, reltol=1e-6)
sol_case1 = rebuild_sol(result_case1)<< @setup-block not executed in draft mode >>julia
df_case1 = DataFrame(:t => sol_case1[:t], :actual => sol_case1[model_case1.vcv.v1])
dfr_case1 = try CSV.read(joinpath(snapshotsdir, "ElectricalComponents.Analog.Basic.Tests.VCV_case1_sig0.ref"), DataFrame); catch e; nothing; end
plt = plot(sol_case1, idxs=[model_case1.vcv.v1], width=2, label="Actual value of vcv.v1")
if !isnothing(dfr_case1)
scatter!(plt, dfr_case1.t, dfr_case1.expected, mc=:red, ms=3, label="Expected value of vcv.v1")
end<< @setup-block not executed in draft mode >>julia
plt<< @example-block not executed in draft mode >>julia
df_case1 = DataFrame(:t => sol_case1[:t], :actual => sol_case1[model_case1.vcv.v2])
dfr_case1 = try CSV.read(joinpath(snapshotsdir, "ElectricalComponents.Analog.Basic.Tests.VCV_case1_sig1.ref"), DataFrame); catch e; nothing; end
plt = plot(sol_case1, idxs=[model_case1.vcv.v2], width=2, label="Actual value of vcv.v2")
if !isnothing(dfr_case1)
scatter!(plt, dfr_case1.t, dfr_case1.expected, mc=:red, ms=3, label="Expected value of vcv.v2")
end<< @setup-block not executed in draft mode >>julia
plt<< @example-block not executed in draft mode >>julia
df_case1 = DataFrame(:t => sol_case1[:t], :actual => sol_case1[model_case1.vcv.i1])
dfr_case1 = try CSV.read(joinpath(snapshotsdir, "ElectricalComponents.Analog.Basic.Tests.VCV_case1_sig2.ref"), DataFrame); catch e; nothing; end
plt = plot(sol_case1, idxs=[model_case1.vcv.i1], width=2, label="Actual value of vcv.i1")
if !isnothing(dfr_case1)
scatter!(plt, dfr_case1.t, dfr_case1.expected, mc=:red, ms=3, label="Expected value of vcv.i1")
end<< @setup-block not executed in draft mode >>julia
plt<< @example-block not executed in draft mode >>julia
df_case1 = DataFrame(:t => sol_case1[:t], :actual => sol_case1[model_case1.vcv.i2])
dfr_case1 = try CSV.read(joinpath(snapshotsdir, "ElectricalComponents.Analog.Basic.Tests.VCV_case1_sig3.ref"), DataFrame); catch e; nothing; end
plt = plot(sol_case1, idxs=[model_case1.vcv.i2], width=2, label="Actual value of vcv.i2")
if !isnothing(dfr_case1)
scatter!(plt, dfr_case1.t, dfr_case1.expected, mc=:red, ms=3, label="Expected value of vcv.i2")
end<< @setup-block not executed in draft mode >>julia
plt<< @example-block not executed in draft mode >>