Detectors.LeadingEdgeDetector

LeadingEdgeDetector(; name)

Detects the rising (leading) edge of a digital signal.

Variables

• u(t): Input signal (boolean, 0 or 1)
• y(t): Output signal (pulse on rising edge)

Description

Detects when the input signal transitions from low (0) to high (1) and produces a single pulse (1.0) at the output for one sampling period. The output remains at 0.0 otherwise.

The component uses a unit delay to store the previous input value and a logical AND operation with the negated previous value to detect the rising edge: y[k] = u[k] AND NOT(u[k-1])

This is useful for triggering events or actions exactly once when a signal becomes active.

Usage

PrimitiveComponents.Detectors.LeadingEdgeDetector()

Connectors

• u - This connector represents a real signal as an input to a component (RealInput)
• y - This connector represents a real signal as an output from a component (RealOutput)

Behavior

\[ \begin{equation} \left[ \begin{array}{c} \mathrm{connect}\left( u(t), memory_{+}u(t), and_{logical\_1_{+}u1(t)} \right) \\ \mathrm{connect}\left( memory_{+}y(t), not_{logical\_1_{+}u(t)} \right) \\ \mathrm{connect}\left( not_{logical\_1_{+}y(t)}, and_{logical\_1_{+}u2(t)} \right) \\ \mathrm{connect}\left( y(t), and_{logical\_1_{+}y(t)} \right) \\ \mathtt{memory.y}\left( t \right) = Shift(t, -1)\left( \mathtt{memory.u}\left( t \right) \right) \\ \frac{\mathrm{d} \mathtt{memory.dummy.l}\left( t \right)}{\mathrm{d}t} = 0 \\ \mathtt{and\_logical\_1.c1}\left( t \right) = check\_with\_target\_value\left( \mathtt{and\_logical\_1.u1}\left( t \right), \mathtt{and\_logical\_1.target\_value}, \mathtt{and\_logical\_1.abs\_tol} \right) \\ \mathtt{and\_logical\_1.c2}\left( t \right) = check\_with\_target\_value\left( \mathtt{and\_logical\_1.u2}\left( t \right), \mathtt{and\_logical\_1.target\_value}, \mathtt{and\_logical\_1.abs\_tol} \right) \\ \mathtt{and\_logical\_1.y}\left( t \right) = ifelse\left( \neg \mathtt{and\_logical\_1.c1}\left( t \right) \wedge \neg \mathtt{and\_logical\_1.c2}\left( t \right), 1, 0 \right) \\ \mathtt{not\_logical\_1.c}\left( t \right) = check\_with\_target\_value\left( \mathtt{not\_logical\_1.u}\left( t \right), \mathtt{not\_logical\_1.target\_value}, \mathtt{not\_logical\_1.abs\_tol} \right) \\ \mathtt{not\_logical\_1.y}\left( t \right) = ifelse\left( \mathtt{not\_logical\_1.c}\left( t \right), 1, 0 \right) \\ \end{array} \right] \end{equation} \]

Source

"""
    LeadingEdgeDetector(; name)

Detects the rising (leading) edge of a digital signal.

# Variables
- `u(t)`: Input signal (boolean, 0 or 1)
- `y(t)`: Output signal (pulse on rising edge)

# Description
Detects when the input signal transitions from low (0) to high (1) and produces
a single pulse (1.0) at the output for one sampling period. The output remains
at 0.0 otherwise.

The component uses a unit delay to store the previous input value and a logical
AND operation with the negated previous value to detect the rising edge:
y[k] = u[k] AND NOT(u[k-1])

This is useful for triggering events or actions exactly once when a signal
becomes active.
"""
component LeadingEdgeDetector
  # Input signal
  u = Dyad.RealInput() {
    "Dyad": {
      "placement": {
        "icon": {"iconName": "default", "x1": -40, "y1": 250, "x2": 0, "y2": 290, "rot": 0},
        "diagram": {"iconName": "default", "x1": -50, "y1": 480, "x2": -10, "y2": 520, "rot": 0}
      }
    }
  }
  # Output signal
  y = Dyad.RealOutput() {
    "Dyad": {
      "placement": {
        "icon": {"iconName": "default", "x1": 1000, "y1": 480, "x2": 1040, "y2": 520, "rot": 0},
        "diagram": {"iconName": "default", "x1": 1000, "y1": 480, "x2": 1040, "y2": 520, "rot": 0}
      }
    }
  }
  memory = PrimitiveComponents.DiscretePrimitives.UnitDelay(ic = 0.0) {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": 210, "y1": 450, "x2": 310, "y2": 550, "rot": 0}
      }
    }
  }
  and_logical_1 = PrimitiveComponents.LogicGates.Logical_AND() {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": 570, "y1": 330, "x2": 670, "y2": 430, "rot": 0}
      }
    }
  }
  not_logical_1 = PrimitiveComponents.LogicGates.Logical_NOT() {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": 410, "y1": 470, "x2": 510, "y2": 570, "rot": 0}
      }
    }
  }
relations
  connect(u, memory.u, and_logical_1.u1) {
    "Dyad": {
      "edges": [
        {"S": 1, "M": [{"x": -30, "y": 477}], "E": -1},
        {"S": -1, "M": [], "E": 2},
        {"S": 3, "M": [{"x": 190, "y": 357}], "E": -1}
      ],
      "junctions": [{"x": 190, "y": 477}]
    }
  }
  connect(memory.y, not_logical_1.u) {
    "Dyad": {"edges": [{"S": 1, "M": [{"x": 389, "y": 500}, {"x": 389, "y": 497}], "E": 2}]}
  }
  connect(not_logical_1.y, and_logical_1.u2) {
    "Dyad": {"edges": [{"S": 1, "M": [{"x": 540, "y": 520}, {"x": 540, "y": 402}], "E": 2}]}
  }
  connect(y, and_logical_1.y) {"Dyad": {"edges": [{"S": 1, "M": [{"x": 1020, "y": 380}], "E": 2}]}}
metadata {
  "Dyad": {
    "labels": [
      {"label": "$(instance)", "x": 500, "y": 1100, "rot": 0},
      {"label": " $(dt_s)", "x": 500, "y": -150, "rot": 0}
    ],
    "icons": {"default": "dyad://PrimitiveComponents/LeadingEdge.svg"}
  }
}
end

"""
    LeadingEdgeDetector(; name)

Detects the rising (leading) edge of a digital signal.

# Variables
- `u(t)`: Input signal (boolean, 0 or 1)
- `y(t)`: Output signal (pulse on rising edge)

# Description
Detects when the input signal transitions from low (0) to high (1) and produces
a single pulse (1.0) at the output for one sampling period. The output remains
at 0.0 otherwise.

The component uses a unit delay to store the previous input value and a logical
AND operation with the negated previous value to detect the rising edge:
y[k] = u[k] AND NOT(u[k-1])

This is useful for triggering events or actions exactly once when a signal
becomes active.
"""
component LeadingEdgeDetector
  # Input signal
  u = Dyad.RealInput() {
    "Dyad": {
      "placement": {
        "icon": {"iconName": "default", "x1": -40, "y1": 250, "x2": 0, "y2": 290, "rot": 0},
        "diagram": {"iconName": "default", "x1": -50, "y1": 480, "x2": -10, "y2": 520, "rot": 0}
      }
    }
  }
  # Output signal
  y = Dyad.RealOutput() {
    "Dyad": {
      "placement": {
        "icon": {"iconName": "default", "x1": 1000, "y1": 480, "x2": 1040, "y2": 520, "rot": 0},
        "diagram": {"iconName": "default", "x1": 1000, "y1": 480, "x2": 1040, "y2": 520, "rot": 0}
      }
    }
  }
  memory = PrimitiveComponents.DiscretePrimitives.UnitDelay(ic = 0.0) {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": 210, "y1": 450, "x2": 310, "y2": 550, "rot": 0}
      }
    }
  }
  and_logical_1 = PrimitiveComponents.LogicGates.Logical_AND() {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": 570, "y1": 330, "x2": 670, "y2": 430, "rot": 0}
      }
    }
  }
  not_logical_1 = PrimitiveComponents.LogicGates.Logical_NOT() {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": 410, "y1": 470, "x2": 510, "y2": 570, "rot": 0}
      }
    }
  }
relations
  connect(u, memory.u, and_logical_1.u1) {
    "Dyad": {
      "edges": [
        {"S": 1, "M": [{"x": -30, "y": 477}], "E": -1},
        {"S": -1, "M": [], "E": 2},
        {"S": 3, "M": [{"x": 190, "y": 357}], "E": -1}
      ],
      "junctions": [{"x": 190, "y": 477}]
    }
  }
  connect(memory.y, not_logical_1.u) {
    "Dyad": {"edges": [{"S": 1, "M": [{"x": 389, "y": 500}, {"x": 389, "y": 497}], "E": 2}]}
  }
  connect(not_logical_1.y, and_logical_1.u2) {
    "Dyad": {"edges": [{"S": 1, "M": [{"x": 540, "y": 520}, {"x": 540, "y": 402}], "E": 2}]}
  }
  connect(y, and_logical_1.y) {"Dyad": {"edges": [{"S": 1, "M": [{"x": 1020, "y": 380}], "E": 2}]}}
metadata {
  "Dyad": {
    "labels": [
      {"label": "$(instance)", "x": 500, "y": 1100, "rot": 0},
      {"label": " $(dt_s)", "x": 500, "y": -150, "rot": 0}
    ],
    "icons": {"default": "dyad://PrimitiveComponents/LeadingEdge.svg"}
  }
}
end

Test Cases

No test cases defined.

Related

• Examples
• Experiments
• Analyses
• Tests
  • Test_LeadingEdgeDetector