Quantization

A quantization block that quantizes the input signal to a specified number of bits.

The output is clamped to the range [y_min, y_max] and quantized to discrete levels. A midrise quantizer does not have a zero output level, while a midtread quantizer does.

This block is not differentiable; the derivative is zero everywhere except at level transitions where it is ill defined. To use in a differentiable context, set quantized = false which turns this block into the identity function.

Parameters:

• y_max: Upper limit of output
• y_min: Lower limit of output
• bits: Number of bits of quantization
• quantized: If quantization effects shall be computed. If false, the output is equal to the input.
• midrise: (structural) If true (default), the quantizer is a midrise quantizer, otherwise it is a midtread quantizer.

Connectors:

• u: Input signal
• y: Output signal

Usage

DiscreteComponents.Quantization(y_max=1, y_min=-1, bits=8, quantized=true)

Parameters:

Connectors

• u - This connector represents a real signal as an input to a component (RealInput)
• y - This connector represents a real signal as an output from a component (RealOutput)

Behavior

using DiscreteComponents #hide
using ModelingToolkit #hide
@variables y_max #hide
@variables y_min #hide
@variables bits #hide
@variables quantized #hide
@named sys = DiscreteComponents.Quantization(y_max=y_max, y_min=y_min, bits=bits, quantized=quantized) #hide
full_equations(sys) #hide

Source

"""
A quantization block that quantizes the input signal to a specified number of bits.

The output is clamped to the range `[y_min, y_max]` and quantized to discrete levels. A midrise quantizer does not have a zero output level, while a midtread quantizer does.

This block is not differentiable; the derivative is zero everywhere except at level transitions where it is ill defined. To use in a differentiable context, set `quantized = false` which turns this block into the identity function.

# Parameters:
- `y_max`: Upper limit of output
- `y_min`: Lower limit of output
- `bits`: Number of bits of quantization
- `quantized`: If quantization effects shall be computed. If false, the output is equal to the input.
- `midrise`: (structural) If true (default), the quantizer is a midrise quantizer, otherwise it is a midtread quantizer.

# Connectors:
- `u`: Input signal
- `y`: Output signal
"""
component Quantization@[input clk extends Discrete]
  "Input signal"
  u = RealInput@[clk]() {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": -100, "y1": 450, "x2": 0, "y2": 550, "rot": 0}
      },
      "tags": []
    }
  }
  "Output signal"
  y = RealOutput@[clk]() {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": 1000, "y1": 450, "x2": 1100, "y2": 550, "rot": 0}
      },
      "tags": []
    }
  }
  "If true, the quantizer is a midrise quantizer, otherwise midtread"
  structural parameter midrise::Boolean = true
  "Upper limit of output"
  parameter y_max::Real = 1
  "Lower limit of output"
  parameter y_min::Real = -1
  "Number of bits of quantization"
  parameter bits::Integer = 8
  "If quantization effects shall be computed"
  parameter quantized::Boolean = true
relations
  y = ifelse(quantized, quantize(u, bits, y_min, y_max, midrise), u)
metadata {"Dyad": {"icons": {"default": "dyad://DiscreteComponents/Quantization.svg"}}}
end

"""
A quantization block that quantizes the input signal to a specified number of bits.

The output is clamped to the range `[y_min, y_max]` and quantized to discrete levels. A midrise quantizer does not have a zero output level, while a midtread quantizer does.

This block is not differentiable; the derivative is zero everywhere except at level transitions where it is ill defined. To use in a differentiable context, set `quantized = false` which turns this block into the identity function.

# Parameters:
- `y_max`: Upper limit of output
- `y_min`: Lower limit of output
- `bits`: Number of bits of quantization
- `quantized`: If quantization effects shall be computed. If false, the output is equal to the input.
- `midrise`: (structural) If true (default), the quantizer is a midrise quantizer, otherwise it is a midtread quantizer.

# Connectors:
- `u`: Input signal
- `y`: Output signal
"""
component Quantization
  "Input signal"
  u = RealInput@[clk]() {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": -100, "y1": 450, "x2": 0, "y2": 550, "rot": 0}
      },
      "tags": []
    }
  }
  "Output signal"
  y = RealOutput@[clk]() {
    "Dyad": {
      "placement": {
        "diagram": {"iconName": "default", "x1": 1000, "y1": 450, "x2": 1100, "y2": 550, "rot": 0}
      },
      "tags": []
    }
  }
  "If true, the quantizer is a midrise quantizer, otherwise midtread"
  structural parameter midrise::Boolean = true
  "Upper limit of output"
  parameter y_max::Real = 1
  "Lower limit of output"
  parameter y_min::Real = -1
  "Number of bits of quantization"
  parameter bits::Integer = 8
  "If quantization effects shall be computed"
  parameter quantized::Boolean = true
relations
  y = ifelse(quantized, quantize(u, bits, y_min, y_max, midrise), u)
metadata {"Dyad": {"icons": {"default": "dyad://DiscreteComponents/Quantization.svg"}}}
end

Test Cases

No test cases defined.

Related

• Examples
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